DIGITAL ELECTRONICS VIRTUAL LAB

4-Bit SISO Shift Register

Serial Input & Serial Output Sequential Logic Simulator

STABLE STATE
SERIAL INPUT:
1.0 Hz
400 ms

4-Bit SISO Shift Register Architecture

D Flip-Flops (Synchronous Common CLK)
HIGH (1) LOW (0) Data Shift Pulse COMMON CLK Line
Synchronous Architecture Rule: Every D Flip-Flop (FF3, FF2, FF1, FF0) receives the SAME active clock edge simultaneously on the COMMON CLK line. On each clock pulse, data transfers sequentially rightward: Serial In ➔ D3 ➔ Q3(D2) ➔ Q2(D1) ➔ Q1(D0) ➔ Q0(Serial Out).

Clock Monitor

Rising Edge (↑)
COMMON CLK LOW
ACTIVE EDGE RISING (↑)
CLOCK SPEED 1.0 Hz
PULSE COUNT 0

Flip-Flop Hardware State Monitor

FF3 (Input Stage / MSB) IDLE
Clock Source: COMMON CLK
Input D3: 0
Output Q3: 0
Output Q3': 1
State: Latched
FF2 (Bit 2) IDLE
Clock Source: COMMON CLK
Input D2: 0
Output Q2: 0
Output Q2': 1
State: Latched
FF1 (Bit 1) IDLE
Clock Source: COMMON CLK
Input D1: 0
Output Q1: 0
Output Q1': 1
State: Latched
FF0 (Output Stage / LSB) IDLE
Clock Source: COMMON CLK
Input D0: 0
Output Q0: 0
Output Q0': 1
State: Latched

State & Shift Monitor

Previous Register 0000
➔
Current Register 0000
➔
Next Register 0000
Input Bit: 0
Shift Direction: RIGHT (FF3 ➔ FF0)
Current Register: 0000
Serial Output (Q0): 0

Real-Time Waveform Timing Diagram

Synchronous Active Clock Edge Signals Rendered
COMMON CLK
SERIAL IN
Q3 (FF3)
Q2 (FF2)
Q1 (FF1)
Q0 (S-OUT)
Observe how data transitions on Q3, Q2, Q1, and Q0 align synchronously with the rising edge of COMMON CLK. Each active clock edge shifts the contents of the register by one bit position to the right.

Shift History Log

Execution Log
Clock # Serial In Q3 Q2 Q1 Q0 Serial Out Register State

Shift Register Configurations Comparison

Configuration Data Entry Data Exit Clock Cycles for 4 Bits Primary Use Cases
SISO (Serial-In Serial-Out) Serial (One bit at a time via single pin) Serial (One bit at a time via Q0) 4 pulses to load, 4 pulses to read out (8 total) Time delay lines, serial data transmission & signal buffering.
SIPO (Serial-In Parallel-Out) Serial (One bit per clock edge) Parallel (Simultaneous Q3..Q0 pins) 4 clock cycles to load all 4 bits Serial-to-parallel conversion, driving LED display buses.
PISO (Parallel-In Serial-Out) Parallel (Loaded simultaneously via D3..D0) Serial (Shifted out bit-by-bit) 1 cycle load + 4 cycles serial shift out Parallel-to-serial conversion, keyboard encoder interfaces.
PIPO (Parallel-In Parallel-Out) Parallel (Instant load) Parallel (Instant read) 1 clock cycle for full load and read Temporary CPU register storage, memory buffer registers.

Educational Theory & Sequential Logic Concepts

What is a Shift Register?

A Shift Register is a cascade of flip-flops connected in series, where data is moved (shifted) from one stage to another on every active clock transition. It can store binary numbers and manipulate serial/parallel data formats.

What is SISO (Serial-In Serial-Out)?

In a SISO Shift Register, data enters the first flip-flop serially (one bit at a time) on each clock edge and exits the final stage serially. To transmit an N-bit binary word, N clock pulses are required to load the word, and N clock pulses are required to shift it out completely.

Data Shifting Mechanics & Clock Role

For a 4-bit right-shift register using D Flip-Flops:

  • Input Stage (FF3): D3 = Serial Input. On clock edge, Q3 ← Serial Input.
  • Stage 2 (FF2): D2 = Q3. On clock edge, Q2 ← Q3.
  • Stage 1 (FF1): D1 = Q2. On clock edge, Q1 ← Q2.
  • Output Stage (FF0): D0 = Q1. On clock edge, Q0 ← Q1.

All flip-flops switch state simultaneously because they share the COMMON CLK signal (Synchronous Operation).

Role of Flip-Flops & Synchronous Timing

Edge-triggered D (Data) Flip-Flops sample their inputs precisely at the active clock edge (rising edge ↑). Because the output state change occurs only after the propagation delay (tpd), the previous state of Qk is captured correctly by Dk-1 before Qk updates. This prevents race conditions during serial shifting.

Practical Engineering Applications & Advantages

Serial Data Transfer Transmitting binary data over single-channel communication lines (e.g., SPI, I2C, USB serializers).
Digital Delay Lines Introducing exact N clock period delays to digital signals in DSP and communication hardware.
Temporary Storage Holding data temporarily while processing or synchronizing between different clock domains.
Embedded Systems Interfacing microcontrollers with low-pin-count serial peripheral ICs and expansion shift registers.
Data Synchronization Aligning asynchronous serial bitstreams to local system clock boundaries.